1. Field of the Invention
The present invention relates to a method for manufacturing a thin-type semiconductor device. Further, the present invention relates to a semiconductor device having a structure in which a semiconductor chip is bonded onto the surface of a solid device (for example, a wiring substrate or another semiconductor chip), and a method for manufacturing the same.
Further, the present invention relates to a semiconductor device which is advantageous to be three-dimensionally packaged and a method for manufacturing the same.
2. Background Art
A back side grinding step for grinding the back side of a semiconductor wafer (hereinafter referred to simply as wafer) in order to thin a semiconductor chip has been conventionally performed. The back side grinding step has been generally performed by adhering a soft protective film onto the surface of a wafer, then urging the wafer against a grinder through the protective film, and rotating the wafer in this state.
However, in a cutting out step for cutting individual semiconductor chips out of the wafer, the wafer is handled by a robot. Further, in a step for mounting each cut-out semiconductor chip on a lead frame, the semiconductor chip is handled by a robot. Therefore, excessive pursuit of thinning of a semiconductor chip causes the wafer or the semiconductor chip to be broken, so that the yield rate is reduced. Especially nowadays, since wafers become large-diametered, wafers thinned by the back side grinding treatment are apt to be broken.
In order to solve these problems, for example, in the Japanese Unexamined Patent Publication (KOKAI) No. 11-150090 (1999), it is proposed that after forming a group of projection electrodes on the surface of a wafer, a resin layer is formed on this surface of the wafer to use the resin layer as a protective and reinforcing plate. According to the method of manufacturing a semiconductor device disclosed in this Publication, after forming a resin layer, the back side of a wafer is ground, and further, the surface layer section of the resin layer is removed by etching. Thereby, the projection electrodes are exposed. Thereafter, the resin layer is removed along a scribed line, and further, a nitride layer as a protective layer is formed in the region avoiding the projection electrodes. Then, the wafer is cut along scribed lines to cut out individual semiconductor chips.
According to this method, a wafer, after its back side being ground, is reinforced by a resin layer, and each semiconductor chip is reinforced by the resin layer. And in each semiconductor chip, the projection electrodes functioning as external connection electrodes are embedded in the resin layer. Thereby, the wafer and the semiconductor chip can be satisfactorily handled without being broken, and at the same time, the semiconductor device can be remarkably thinned in comparison with a structure in which outer terminals are pulled out by wire-bonding or the like.
However, it is necessary to perform etching in order to expose the projection electrodes. At the time of etching, etching conditions must be determined so as to surely expose all of the projection electrodes, and therefore, the etching step is complicated and takes much time.
Furthermore, according to the above-mentioned manufacturing method of the prior art, there is a problem that a wafer is warped because of the differences between the thermal expansion/contraction coefficients of the wafer and the resin layer during the time after forming the resin layer on the wafer and before grinding the back side of the wafer. Such a warped wafer is exaggeratedly shown in FIG. 18. When such a warped wafer is ground by a flat grinder, the wafer after being ground has different thicknesses at the central region and the peripheral region thereof respectively. Consequently, semiconductor chips each having a uniform thickness cannot be obtained and in addition, sometimes a semiconductor chip cut out of the central region of the wafer may not be thinned to a desired thickness.
On the other hand, one of structures capable of heightening the substantial integration density of a semiconductor device is a chip-on-chip structure. In a semiconductor device having a chip-on-chip structure, for example, as shown in FIG. 19, a secondary chip 102 is bonded face-down onto the surface of a primary chip 101, and external connection electrodes 103 are provided on the back side of the primary chip 101. Such a chip-on-chip structure is advantageous to obtain a high integration density of the elements. However, in addition to the thicknesses a, b of the primary chip 101 and the secondary chip 102, the height c of the external connection electrodes is required. Therefore, it is a defect that the whole height (a+b+c) becomes relatively high.
Further, it is proposed that the space occupied by a semiconductor device is reduced by thinning a semiconductor package and three-dimensionally packaging or mounting the same.
FIG. 20 is a sectional view showing an example of a structure of a semiconductor device 70 proposed for the above-mentioned purpose. In the semiconductor device 70, a thin semiconductor chip 72 is disposed in a punched portion of a tape-shaped substrate 71, and the active surface (the upper surface in FIG. 20) of the semiconductor chip 72 is sealed with a protective resin 73. Inner leads 74 are connected to the semiconductor chip 72 by single point bonding. The connection between the semiconductor chip 72 and an outer packaging substrate 80 is achieved by outer leads 75 connected to the inner leads 74 on the substrate 71. The three-dimensional packaging of the semiconductor device 70 is performed by connecting the outer leads 75 to the packaging substrate 80 respectively.
However, in this structure, it is necessary to individually connect outer leads 75 of each semiconductor device 70 to the packaging substrate 80. Therefore, the three-dimensional packaging steps are complicated and hard to perform.
Further, in this structure, since the outer leads 75 are pulled outwardly, there is a problem that the area occupied by the whole of the semiconductor device 70 becomes relatively large.